Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof
US7863735B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Aug 7, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a tiered encapsulant above the base substrate, the tiered encapsulant having a first cavity above the base substrate and a second cavity above the first cavity adjacent an intermediate horizontal side; connecting an intermediate interconnect to the base substrate, the intermediate interconnect surrounded by the tiered encapsulant and substantially exposed on the intermediate horizontal side; and connecting a top interconnect to the base substrate, the top interconnect surrounded by the tiered encapsulant and substantially exposed on a top horizontal side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.