Inventor · Suneung-ri, KR

HeeJo Chi

85Patents

17h-index

50Co-inventors

79Inventor score

Filing activity: Mar 5, 2009 → Dec 18, 2017

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8264091B2	Integrated circuit packaging system with encapsulated via and method of manufacture thereof	Electricity	94	Active
US7928552B1	Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof	Electricity	93	Active
US8143097B2	Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP	Electricity	58	Active
US9735113B2	Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP	Electricity	48	Active
US8039316B2	Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof	Electricity	47	Active
US9362161B2	Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package	Electricity	47	Active
US9397050B2	Semiconductor device and method of forming pre-molded semiconductor die having bumps embedded in encapsulant	Electricity	45	Active
US8390108B2	Integrated circuit packaging system with stacking interconnect and method of manufacture thereof	Electricity	44	Active
US8288209B1	Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die	Electricity	41	Active
US9496152B2	Carrier system with multi-tier conductive posts and method of manufacture thereof	Emerging Cross-Sectional Technologies	41	Active
US8106498B2	Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof	Electricity	37	Active
US8318539B2	Method of manufacture of integrated circuit packaging system with multi-tier conductive interconnects	Electricity	36	Active
US8138014B2	Method of forming thin profile WLCSP with vertical interconnect over package footprint	Electricity	33	Active
US9048306B2	Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP	Electricity	27	Active
US7863735B1	Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof	Emerging Cross-Sectional Technologies	23	Active
US8471394B2	Integrated circuit packaging system with package-on-package and method of manufacture thereof	Electricity	22	Active
US9391046B2	Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor wafer	Electricity	18	Active
US8035235B2	Integrated circuit packaging system with package-on-package and method of manufacture thereof	Electricity	17	Active
US9330994B2	Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring	Electricity	16	Active
US8357564B2	Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die	Electricity	15	Active
US8202797B2	Integrated circuit system with recessed through silicon via pads and method of manufacture thereof	Electricity	14	Active
US8409917B2	Integrated circuit packaging system with an interposer substrate and method of manufacture thereof	Electricity	14	Active
US9875911B2	Semiconductor device and method of forming interposer with opening to contain semiconductor die	Electricity	12	Active
US8716065B2	Integrated circuit packaging system with encapsulation and method of manufacture thereof	Electricity	11	Active
US9252130B2	Methods of manufacturing flip chip semiconductor packages using double-sided thermal compression bonding	Electricity	10	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.