Patent · US Active

Integrated circuits having a controller to control a read operation and methods for operating the same

US7864579B2 · kind B2 · utility

10Cited by

2References

4Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Jan Gutsche · Munich, DE
Michael Scheppler · Gröbenzell, DE
Gert Koebernik · Unterhaching, DE
Detlev Richter · Unterhaching, DE

Key dates

Filing date	Jul 24, 2008
Grant date	Jan 4, 2011
Priority date	—
Expiry date	Dec 19, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/76
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a memory cell block having a plurality of memory cells, a storage portion configured to store information about a quality characteristic of the memory cells of the memory cell block, and a controller configured to control a read operation, and to change the information about the quality characteristic depending on a quality of a read operation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.