Recovery method of NAND flash memory device
US7864581B2 · kind B2 · utility
4Cited by
2References
7Claims
0Family size
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Inventor
Key dates
| Filing date | Dec 7, 2005 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Dec 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory device is recovered by applying a predetermined bias to a drain or a source. A negative bias is applied to a cell gate so that electrons are injected into a floating gate of a cell. This narrows the distribution of an erase threshold voltage and minimizes interference from states of peripheral cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.