Memory with reduced power supply voltage for a write operation
US7864617B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Jul 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a selection circuit and a write assist circuit. The selection circuit has a first input, a second input coupled to a first power supply voltage terminal, an output coupled to a power supply terminal of each of a plurality of memory cells, and a control input for receiving a write assist control signal. The write assist circuit is coupled to the first input of the selection circuit for reducing a voltage at the power supply terminal of each of the plurality of memory cells during a write operation and in response to an asserted write assist enable signal. The write assist circuit comprises a P-channel transistor and a bias voltage generator. The P-channel transistor is for reducing the voltage at the power supply terminal of each of the plurality of memory cells during the write operation. The bias voltage generator is for providing a variable bias voltage to the P-channel transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.