Hybrid transistor based power gating switch circuit and method

US7867858B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Giri Nallapati · Austin, US
• Sushama Davar · Santa Clara, US
• Robert E. Booth · Austin, US
• Michael P. Woo · Austin, US
• Mahbub Rashed · Cupertino, US

Key dates

• Filing date: Mar 31, 2008
• Grant date: Jan 11, 2011
• Expiry date: Apr 25, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0144

Abstract

A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.