Set algorithm for phase change memory cell
US7869270B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2008 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Jul 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.