Dynamic processor power management device and method thereof
US7870407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2007 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Jun 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.