Patent · US Active

System-on-chip with master/slave debug interface

US7870455B2 · kind B2 · utility

26Cited by

8References

19Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventor

Albrecht Mayer · Deisenhofen, DE

Key dates

Filing date	Dec 12, 2007
Grant date	Jan 11, 2011
Priority date	—
Expiry date	Nov 19, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/18
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface and a user interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system. The host system is connected to the at least one of the plurality of SOC ICs via the user interface.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.