Stress free package and laminate-based isolator package
US7871865B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2007 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Jul 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various methods are described where the semiconductor die and the lead frame (or the BGA or LGA substrate) are spaced apart to reduce stress. In one scenario, an air gap is formed between the semiconductor die and the lead frame by depositing a perimeter (made, for example, using polymer) either on the semiconductor die or the lead frame. In another scenario, an anisotropic conducting film (ACF) is formed with an air gap between the semiconductor die and the lead frame (or the BGA or LGA substrate). The air gap relieves stress on the semiconductor die. Further, a lead frame-based isolator package and a BGA (or LGA) isolator package are described. A window-frame ACF-based isolation method for magnetic coupling in a lead-frame package and BGA (or LGA) package is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.