Transistor of semiconductor device and method of fabricating the same
US7871874B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2009 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Mar 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/4738
Abstract
Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a hig…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.