Method for fabricating buried capacitor structure
US7871892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2009 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Sep 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1461
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.