Method for manufacturing semiconductor device having vertical transistor
US7871913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2008 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Feb 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
Abstract
A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.