Delay locked loop circuit
US7872508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2009 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Jun 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop circuit includes a delay locking block configured to delay an input clock and output the delayed input clock as an internal clock to compensate a skew of an external clock and the internal clock, a pulse generating block configured to sequentially output a plurality of pulse signals that control an operation of the delay locking block and enable one of the plurality of pulse signals in response to a detection signal, wherein the plurality of pulse signals is shifted by being synchronized with the input clock, and a pulse detecting block configured to output the detection signal in case all of the plurality of pulse signals are disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.