Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion
US7873810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2004 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | May 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3552
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A modular subtraction instruction for execution on a microprocessor having at least one register. The instruction includes opcode bits for designating the instruction and operand bits for designating at least one register storing an offset index, a decrement value, and an address index. When the modular subtraction instruction is executed on the microprocessor, the address index is modified by the decrement value if the address index is not zero and is modified by the offset index if the address index is zero. For example, the address index is repeatedly decremented using the decrement value until it reaches zero, and then the address index is reset back to the offset index. The operand bits may include multiple fields identifying multiple registers selected from the general purpose registers of the microprocessor. The modular subtraction instruction enables access to a buffer in memory in circular fashion by virtue of its operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.