Method of manufacturing a semiconductor package
US7875497B2 · kind B2 · utility
5Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2009 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Dec 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming a cavity by etching a center portion of a metal oxide layer; mounting a second chip inside the cavity; forming at least one via such that the via penetrates an edge of the metal oxide layer; placing the metal oxide layer on the first substrate such that the second chip and the first chip face each other; and placing a second substrate on the metal oxide layer, the second substrate having a third chip mounted thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.