Strain-silicon CMOS using etch-stop layer and method of manufacture

US7875543B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Yuhao Luo · San Jose, US
• Deepak Nayak · Kanchinakote, IN

Key dates

• Filing date: Aug 28, 2008
• Grant date: Jan 25, 2011
• Expiry date: May 23, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide strain in the plane of the channel region. In a particular embodiment, a tensile silicon nitride layer is formed over recesses of an NMOS transistor in a CMOS cell, and a compressive silicon nitride layer is formed over recesses of a PMOS transistor in the CMOS cell. In a particular embodiment the stressed silicon nitride layer(s) is a chemical etch stop layer.