Memory controller prioritization scheme
US7877558B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2007 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Aug 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.