System and method to optimize semiconductor power by integration of physical design timing and product performance measurements

US7877714B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Theodoros E. Anemikos · Colchester, US
• Jeanne P. Spence Bickford · South Burlington, US
• Laura S. Chadwick · South Burlington, US
• Susan K. Lichtensteiger · South Burlington, US
• Anthony D. Polson · Jericho, US

Key dates

• Filing date: Feb 27, 2008
• Grant date: Jan 25, 2011
• Expiry date: Jan 31, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/3008
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.