Fill-in etching free pore device
US7879645B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 28, 2008 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Jul 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.