Method of providing protection against charging damage in hybrid orientation transistors

US7879650B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Terence B. Hook · Jericho, US
• Anda C. Mocuta · Hopewell Junction, US
• Jeffrey W. Sleight · Ridgefield, US
• Anthony K. Stamper · Williston, US

Key dates

• Filing date: Dec 19, 2007
• Grant date: Feb 1, 2011
• Expiry date: Apr 23, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601

Abstract

In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction path in a SOI layer, i.e., a semiconductor layer that is separated from the bulk region by a buried dielectric region. The crystal orientations of the SOI layer and the bulk region can be different. A first diode can be formed in a second region of the substrate in conductive communication with the bulk region. The first diode may be connected in a reverse-biased orientation to a first gate conductor above the SOI layer, such that a voltage on the gate conductor that exceeds the breakdown voltage can be discharged through the first diode to the bulk region of the substrate. A second diode may be formed in a third region of the substrate in conductive communication with the bulk region. The second diode may be connected in a reverse-biased orientation to a source region or a drain region of an NFET.