Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length

US7879669B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Chih Sieh Teng · San Jose, US
• Constantin Bulucea · Milpitas, US
• Chin-Miin Shyu · San Jose, US
• Fu-Cheng Wang · 東區, TW
• Prasad Chaparala · Sunnyvale, US

Key dates

• Filing date: Sep 25, 2006
• Grant date: Feb 1, 2011
• Expiry date: Sep 25, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 μm greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 μm greater than LC.