Patterning nanocrystal layers
US7879673B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2009 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | May 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with first and second regions with a first device layer. A second device layer including nanocrystals is also formed. A cover layer is provided over the second device layer. The cover layer is patterned to expose portions of the second device layer in the first and second regions. The exposed portions of the second device layer in the first and second regions are processed to form modified portions. The processing of the exposed portions at least reduces the nanocrystals to a diameter below a threshold diameter in the modified portions. The modified portions are removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.