Method of fabricating a semiconductor device including a pattern of line segments

US7879727B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Sergei Postnikov · Grenoble, FR
• Thomas Schulz · Austin, US
• Hans-Joachim Barth · Munich, DE
• Klaus von Arnim · Herzhorn, DE

Key dates

• Filing date: Jan 15, 2009
• Grant date: Feb 1, 2011
• Expiry date: May 23, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32139
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.