Charge trapping dielectric structure for non-volatile memory
US7879738B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2006 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Sep 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
Abstract
An integrated circuit structure comprises a bottom dielectric layer on a substrate, a middle dielectric layer, and a top dielectric layer. The middle dielectric layer has a top surface and a bottom surface, and comprises a plurality of materials. Respective concentration profiles for at least two of the plurality of materials between the top and bottom surfaces are non-uniform and arranged to induce a variation in energy gap between the top and bottom surfaces. The variation in energy gap establishes an electric field between the top and bottom surfaces tending to oppose charge motion toward at least one of the top and bottom surfaces and prevent resultant charge leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.