Latch-up free vertical TVS diode array structure using trench isolation
US7880223B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2006 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Apr 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.