Spacer structure in MRAM cell and method of its fabrication
US7880249B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2005 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Jan 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
Abstract
Methods are presented for fabricating an MTJ element having a precisely controlled spacing between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each method forms a dielectric spacer layer on the lateral sides of the MTJ element and, depending on the method, includes an additional layer that protects the spacer layer during etching processes used to form a Cu damascene bit line. At various stages in the process, a dielectric layer is also formed to act as a CMP stop layer so that the capping layer on the MTJ element is not thinned by the CMP process that planarizes the surrounding insulation. Subsequent to planarization, the stop layer is removed by an anisotropic etch of such precision that the MTJ element capping layer is not thinned and serves to maintain an exact spacing between the bit line and the MTJ free layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.