Integrated circuit selective scaling
US7882463B2 · kind B2 · utility
7Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2008 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Mar 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.