Chip stacked structure and the forming method
US7888172B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Dec 9, 2008 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Dec 9, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure is provided, includes a chip that having a plurality of pads and an adhesive layer on the back side; an encapsulated structure is covered around the four sides of the chip to expose the pads, and the through holes is formed within the encapsulated structure; a patterned first protective layer is formed on the portion surface of encapsulated structure, the portion of active surface of the chips, and the pads of the chip and the through holes are to be exposed; a metal layer is formed on the portion surface of the patterned first protective layer and formed to electrically connect the pads and to fill with the through holes; the patterned second protective layer is formed on the patterned first protective layer and the portion of metal layer, and the portion surface of metal layer is to be exposed; a patterned UBM layer is formed on the exposed surface of the metal layer and the portion surface of the patterned second protective layer; and the conductive elements is formed on the patterned UBM layer and electrically connect to the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.