Stacked integrated circuit assembly

US7888176B2 · kind B2 · utility

Assignee

• Raytheon Company · US

Inventors

• Tse E. Wong · Los Alamitos, US
• Samuel D. Tonomura · Rancho Palos Verdes, US
• Stephen E. Sox · Tustin, US
• Timothy E. Dearden · Torrance, US
• Clifton Quan · Arcadia, US
• Polwin C. Chan · Monterey Park, US
• Mark S. Hauhe · Hermosa Beach, US

Key dates

• Filing date: Sep 10, 2009
• Grant date: Feb 15, 2011
• Expiry date: Sep 10, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.