Patent · US Active

Method for etching silicon-containing ARC layer with reduced CD bias

US7888267B2 · kind B2 · utility

5Cited by

2References

20Claims

0Family size

Assignee

TOKYO ELECTRON LIMITED · JP

Inventors

Akiteru Ko · Schenectady, US
Christopher Cole · Gloucester, GB

Key dates

Filing date	Feb 1, 2008
Grant date	Feb 15, 2011
Priority date	—
Expiry date	Nov 2, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/67109
WIPO fieldElectrical machinery, apparatus, energy
WIPO sectorElectrical engineering

Abstract

A method of dry developing a multi-layer mask having a silicon-containing anti-reflective coating (ARC) layer on a substrate is described. The method comprises forming the multi-layer mask on the substrate, wherein the multi-layer mask comprises a lithographic layer overlying the silicon-containing ARC layer. A feature pattern is then formed in the lithographic layer using a lithographic process. Thereafter, the feature pattern is transferred from the lithographic layer to the silicon-containing ARC layer using a dry plasma etching process, wherein the offset in the critical dimension (CD) bias is reduced between nested structures and isolated structures.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.