Akiteru Ko
57Patents
9h-index
54Co-inventors
77Inventor score
Filing activity: May 25, 2004 → Aug 15, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10354873B2 | Organic mandrel protection process | Electricity | 324 | Active |
| US9786503B2 | Method for increasing pattern density in self-aligned patterning schemes without using hard masks | Electricity | 39 | Active |
| US9673059B2 | Method for increasing pattern density in self-aligned patterning integration schemes | Electricity | 39 | Active |
| US8735291B2 | Method for etching high-k dielectric using pulsed bias power | Electricity | 37 | Active |
| US9570313B2 | Method for etching high-K dielectric using pulsed bias power | Electricity | 37 | Active |
| US9159575B2 | Method for etching high-K dielectric using pulsed bias power | Electricity | 35 | Active |
| US10290506B2 | Method for etching high-K dielectric using pulsed bias power | Electricity | 35 | Active |
| US9443731B1 | Material processing to achieve sub-10nm patterning | Electricity | 17 | Active |
| US8334083B2 | Etch process for controlling pattern CD and integrity in multi-layer masks | Electricity | 14 | Active |
| US9165765B1 | Method for patterning differing critical dimensions at sub-resolution scales | Electricity | 9 | Active |
| US8236700B2 | Method for patterning an ARC layer using SF6 and a hydrocarbon gas | Electricity | 8 | Active |
| US7888267B2 | Method for etching silicon-containing ARC layer with reduced CD bias | Electricity | 5 | Active |
| US8945408B2 | Etch process for reducing directed self assembly pattern defectivity | Electricity | 4 | Active |
| US8268184B2 | Etch process for reducing silicon recess | Electricity | 4 | Active |
| US9257280B2 | Mitigation of asymmetrical profile in self aligned patterning etch | Electricity | 3 | Active |
| US8980111B2 | Sidewall image transfer method for low aspect ratio patterns | Electricity | 3 | Active |
| US9899219B2 | Trimming inorganic resists with selected etchant gas mixture and modulation of operating variables | Electricity | 3 | Active |
| US7531461B2 | Process and system for etching doped silicon using SF6-based chemistry | Electricity | 2 | Expired |
| US9520270B2 | Direct current superposition curing for resist reflow temperature enhancement | Performing Operations; Transporting | 2 | Active |
| US7743731B2 | Reduced contaminant gas injection system and method of using | Electricity | 2 | Active |
| US9812325B2 | Method for modifying spacer profile | Emerging Cross-Sectional Technologies | 2 | Active |
| US9153457B2 | Etch process for reducing directed self assembly pattern defectivity using direct current positioning | Performing Operations; Transporting | 1 | Active |
| US10217670B2 | Wrap-around contact integration scheme | Electricity | 1 | Active |
| US10260150B2 | Method and system for sculpting spacer sidewall mask | Electricity | 1 | Active |
| US8501628B2 | Differential metal gate etching process | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.