Patent · US Active

Apparatus and method configured to lower thermal stresses

US7888782B2 · kind B2 · utility

2Cited by

4References

21Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Nelle · Munich, DE
Matthias Stecher · Munich, DE

Key dates

Filing date	Oct 26, 2007
Grant date	Feb 15, 2011
Priority date	—
Expiry date	Jan 15, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/351
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.