Apparatus and method for hardening latches in SOI CMOS devices

US7888959B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ethan H. Cannon · South Burlington, US
• AJ KleinOsowski · Austin, US
• K. Paul Muller · Wappingers Falls, US
• Tak H. Ning · Yorktown Heights, US
• Philip J. Oldiges · Lagrangeville, US
• Leon Sigal · Monsey, US
• James D. Warnock · Somers, US
• Dieter Wendel · Schenefeld, DE

Key dates

• Filing date: Sep 19, 2007
• Grant date: Feb 15, 2011
• Expiry date: Feb 6, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K3/0375
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.