Test circuit for performing multiple test modes
US7890286B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 2, 2009 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Jun 2, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.