Processor comprising a first and a second mode of operation and method of operating the same
US7890740B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 2007 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Nov 6, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprises a first mode of operation and a second mode of operation. A state of the processor in the first mode of operation comprises a first plurality of variables. The first plurality of variables comprises a return address. A state of the processor in the second mode of operation comprises a second plurality of variables in addition to the first plurality of variables. The processor is configured to perform, in case of an interrupt or exception occurring during the second mode of operation, the steps of saving the second plurality of variables and the return address to a buffer memory, replacing the return address with an address of a trampoline instruction, and switching into the first mode of operation. These steps are performed independently of an operating system. The trampoline instruction is adapted to switch the processor from the first mode of operation to the second mode of operation, to read the second plurality of variables and the return address from the buffer memory and to jump to the return address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.