Patent · US Active

Method and system for verifying the equivalence of digital circuits

US7890901B2 · kind B2 · utility

7Cited by

1References

15Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Tobias Gemmeke · Santa Clara, US
Jens Leenstra · Nagold, DE
Nicolas Maeding · Holzgerlingen, DE
Hari Mony · Austin, US

Key dates

Filing date	Mar 12, 2007
Grant date	Feb 15, 2011
Priority date	—
Expiry date	Apr 7, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/3323
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.