Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells
US7890906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2008 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Jan 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.