HVNMOS structure for reducing on-resistance and preventing BJT triggering

US7893490B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Yu-Hui Huang · Ann Arbor, US
• Ting Li · Ventura, US
• Fu-Hsin Chen · Hsinchu, TW

Key dates

• Filing date: Apr 30, 2007
• Grant date: Feb 22, 2011
• Expiry date: Sep 5, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/152

Abstract

A high-voltage metal-oxide-semiconductor (HVMOS) device and methods for forming the same are provided. The HVMOS device includes a substrate; a first high-voltage n-well (HVNW) region buried in the substrate; a p-type buried layer (PBL) horizontally adjoining the first HVNW region; a second HVNW region on the first HVNW region; a high-voltage p-well (HVPW) region over the PBL; an insulating region at a top surface of the second HVNW region; a gate dielectric extending from over the HVPW region to over the second HVNW region, wherein the gate dielectric has a portion over the insulating region; and a gate electrode on the gate dielectric.