Concurrent buffering and layer assignment in integrated circuit layout
US7895557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2008 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | May 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the “slack” gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.