Patent · US Active

Method for encapsulating a high-K gate stack by forming a liner at two different process temperatures

US7897450B2 · kind B2 · utility

7Cited by

3References

8Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Fabian Koehler · Valley, DE
Katy Schabernack · Spremberg - Grodk, DE
Falk Graetsch · Dresden, DE

Key dates

Filing date	Jan 16, 2009
Grant date	Mar 1, 2011
Priority date	—
Expiry date	Jan 16, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/601
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.