Critical path redundant logic for mitigation of hardware across chip variation

US7898286B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Igor Arsovski · Williston, US
• Hayden C. Cranford, Jr. · Cary, US
• Joseph A. Iadanza · South Burlington, US
• Todd E. Leonard · Williston, US
• Jason M. Norman · South Burlington, US
• Hemen R. Shah · South Burlington, US
• Sebastian T. Ventrone · South Burlington, US

Key dates

• Filing date: Feb 11, 2009
• Grant date: Mar 1, 2011
• Expiry date: Feb 11, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31725
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.