Methods for fabricating a stressed MOS device
US7902008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2005 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | May 7, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/938
Abstract
A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.