Field programmable gate array utilizing dedicated memory stacks in a vertical layer format
US7902879B2 · kind B2 · utility
4Cited by
13References
32Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 16, 2009 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Dec 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.