Integrated circuit, memory cell array, memory module, and method of operating an integrated circuit
US7903454B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 2, 2008 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Sep 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1659
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.