Integrated circuit having memory with configurable read/write operations and method therefor
US7903483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2008 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Jan 31, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion of the memory; changing the first access margin to a second access margin, the second access margin being different than the first access margin; determining that the error is corrected with the first portion having the second access margin; and storing an access assist bit in a first storage element, the access assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished at the second access margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.