Structure for power-efficient cache memory
US7904658B2 · kind B2 · utility
16Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2007 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Aug 13, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure for a cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.