Activating a design test mode in a graphics card having multiple execution units to bypass a host cache and transfer test instructions directly to an instruction cache
US7904701B2 · kind B2 · utility
1Cited by
16References
12Claims
0Family size
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Key dates
| Filing date | Jun 7, 2007 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Sep 8, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.