Lance Cheney
12Patents
3h-index
14Co-inventors
53Inventor score
Filing activity: May 21, 2007 → Sep 20, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10803548B2 | Disaggregation of SOC architecture | Emerging Cross-Sectional Technologies | 19 | Active |
| USD592319S1 | Textured architectural panel | General | 4 | Expired |
| US7793187B2 | Checking output from multiple execution units | Physics | 4 | Active |
| US11410266B2 | Disaggregation of System-On-Chip (SOC) architecture | Emerging Cross-Sectional Technologies | 2 | Active |
| US10909652B2 | Enabling product SKUs based on chiplet configurations | Physics | 2 | Active |
| US11386521B2 | Enabling product SKUS based on chiplet configurations | Physics | 1 | Active |
| US7904701B2 | Activating a design test mode in a graphics card having multiple execution units to bypass a host cache and transfer test instructions directly to an instruction cache | Physics | 1 | Active |
| US12056789B2 | Disaggregation of system-on-chip (SOC) architecture | Emerging Cross-Sectional Technologies | 0 | Active |
| US12141890B2 | Enabling product SKUs based on chiplet configurations | Physics | 0 | Active |
| US12112398B2 | Disaggregation of system-on-chip (SOC) architecture | Emerging Cross-Sectional Technologies | 0 | Active |
| US11763416B2 | Disaggregation of system-on-chip (SOC) architecture | Emerging Cross-Sectional Technologies | 0 | Active |
| US11756150B2 | Disaggregation of system-on-chip (SOC) architecture | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.