Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur
US7904891B2 · kind B2 · utility
2Cited by
46References
34Claims
0Family size
Inventors
Key dates
| Filing date | Jul 22, 2008 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Jul 22, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.